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Si5040
Table 8. AC Characteristics—I 2 C Bus Lines (SD, SCK)
(V DD = 1.8 V +5/–10%, T A = –40 to 95 ? C)
Parameter
Pin Capacitance
Symbol
C II2C
Test Condition
Min
—
Typ
—
Max
10
Unit
pF
Table 9. Switching Characteristics—Serial Microcontroller Interface 2
V DD = 1.8 V +5/–10%, V DDIO = 3.3 V ±10%, T A = –40 to 95 °C, C L = 20 pF
Parameter
Symbol
Test
Min
Typ
Max
Unit
Conditions
Cycle Time SCK
t c
100
—
—
ns
Rise Time, SCK
Fall Time, SCK
Low Time, SCK
High Time, SCK
Delay Time, SCK Fall to SD Active
Delay Time, SCK Fall to SD Transition
t r
t f
t lsc
t hsc
t d1
t d2
20–80%
20–80%
20–20%
80–80%
—
—
30
30
—
—
—
—
—
—
—
—
25
25
—
—
25
25
ns
ns
ns
ns
ns
ns
Delay Time, SS Rise to SD Tri-state
Setup Time, SS to SCK Fall
Hold Time, SS to SCK Rise
Setup Time, SD to SCK Rise
Hold Time, SD to SCK Rise
Delay Time between Slave Selects
1
t d3
t su1
t h1
t su2
t h2
t cs
—
25
20
25
20
25
—
—
—
—
—
—
25
—
—
—
—
—
ns
ns
ns
ns
ns
ns
Notes:
1. SD is designed to be tristated by the release of the chip select signal (the rising edge of the SS).
2. All timing is referenced to the 50% level of the waveform unless otherwise noted. Input test levels are V IH = V DD –0.4 V,
V IL = 0.4 V
14
Rev. 1.3
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